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FEATURES Programmable Sinusoidal Oscillator Synthesized Synchronous Reference Output Programmable Output Frequency Range: 2 kHz-20 kHz "Loss-of-Signal" Indicator 20-Pin PLCC Package Low Cost APPLICATIONS Excitation Source for: Resolvers Synchros LVDTs RVDTs Pressure Transducers Load Cells AC Bridges
FBIAS SEL1 SEL2 FREQUENCY SELECT
Programmable Oscillator AD2S99
FUNCTIONAL BLOCK DIAGRAM
PUSH/ PULL O/P STAGE EXC EXC TO TRANSDUCER
SINE WAVE GENERATOR SYNREF SYNCHRONOUS REFERENCE LOS
AD2S99
PHASE DETECT LOGIC
SIN
COS
FROM TRANSDUCER
GENERAL DESCRIPTION
The AD2S99 programmable sinusoidal oscillator provides sine wave excitation for resolvers and a wide variety of ac transducers. The AD2S99 also provides a synchronous reference output signal (3 V p-p square wave) that is phase locked to its SIN and COS inputs. In an application, the SIN and COS inputs are connected to the transducer's secondary windings. The synchronous reference output compensates for temperature and cabling dependent phase shifts and eliminates the need for external preset phase compensation circuits. The synchronous reference output can be used as a zero crossing reference for resolver-to-digital converters such as Analog Devices' AD2S80A, AD2S82A, AD2S83 and AD2S90. The AD2S99 is packaged in a 20-pin PLCC and operates over -40C to +85C.
PRODUCT HIGHLIGHTS Dynamic Phase Compensation
The AD2S99 dynamically compensates for any phase variation in a transducer by phase locking its synchronous reference output to the transducer's secondary windings.
Programmable Excitation Frequency
The excitation frequency is easily programmed to 2 kHz, 5 kHz, 10 kHz, or 20 kHz by using the frequency select pins. Intermediate frequencies are available by adding an external resistor.
Signal Loss Detection
The AD2S99 has the ability to detect if both the transducer secondary winding connections become disconnected from its SIN and COS inputs. The "LOS" output pin pulls high when a signal loss is detected.
Integration
The AD2S99 integrates the transducer excitation, synchronous reference, and loss of signal detection functions into a small, cost effective package.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD2S99-SPECIFICATIONS (V =
S
4.75 V to
Typ 2000 5000 10000 20000
5.25 V @ -40 C to +85 C unless otherwise noted)
Max Units Hz Hz Hz Hz 10 20 5 10 % % % % % % % % V p-p/V Test Conditions SEL1 VSS VSS GND GND SEL2 VSS GND VSS GND
Parameter FREQUENCY OUTPUT RANGE 2 kHz 5 kHz 10 kHz 20 kHz ACCURACY Frequency
Min
AP Grade @ +25C AP Grade -40C to +85C BP Grade @ +25C BP Grade -40C to +85C AP Grade @ +25C AP Grade -40C to +85C BP Grade @ +25C BP Grade -40C to +85C Output Variation as Function of Change in Power Supply Voltage
Amplitude
3 3
10 20 5 10
Power Supply Rejection Ratio ANALOG OUTPUTS Amplitude EXC, EXC SYNREF SYNREF OFFSET Current Drive Capability EXC, EXC VS = 5 V Capacitive Drive Total Harmonic Distortion EXC, EXC ANALOG INPUTS SIN, COS Amplitude Phase Lock Range Additional Phase Delay 1.8 -45
0.002
2 3
200 8 1000
V rms V p-p mV mA rms pF dB
EXC to GND, EXC to GND Square Wave RLOAD = 500 EXC to EXC CLOAD = 1000 pF
-25 2.0 2.2 +45 10 10 VSS AGND 0.7 VDD 0.5 +4.75 -4.75 0.6 0.8 +5.25 -5.25 15 +85 +150
V rms Degrees Degrees Degrees V dc V dc V dc V rms V dc V dc mA C C IOL = 400 A 50 k Pull Up to VDD (Open Drain Output) AP Grade BP Grade
FREQUENCY SELECT INPUTS SEL1, SEL21 LOS OUTPUT Output Low Voltage Output High Voltage SIN, COS LOS Threshold POWER SUPPLIES VDD VSS Quiescent Current IDD, ISS TEMPERATURE RANGE Operating Storage
8
No Load
-40 -65
NOTES 1 Frequency select pins SEL1 and SEL2 must be connected to appropriate voltage levels before power is applied. Specifications subject to change without notice.
-2-
REV. B
AD2S99
ABSOLUTE MAXIMUM RATINGS* PIN DESIGNATIONS
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V Operating Temperature . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Analog Input Voltages (SIN and COS) . . . . . . . . . VSS - 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to VDD + 0.3 V Frequency Select (SEL1, SEL2) . . . . . . . . . . . . . . VSS - 0.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND + 0.4 V
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin No. 1 2 3 5 61 7 10 11 12 161 17 18 192 202
Mnemonic SEL2 SEL1 FBIAS SIN DGND COS SYNREF LOS VDD AGND EXC EXC VSS VSS
Description Frequency Select 2 Frequency Select 1 External Frequency Adjust Pin Resolver Output SIN Digital Ground Resolver Output COS Synthesized Reference Output Indicates When Both the SIN and COS Are Below the Threshold. Positive Power Supply Analog Ground Resolver Reference One Resolver Reference Two3 Negative Power Supply Negative Power Supply
Power Supply Voltage (VDD to VSS) . . . . . . 4.75 V to 5.25 V Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms 10% Frequency Select (SEL1 and SEL2) . . . . . . . . . VSS to AGND Operating Temperature Range . . . . . . . . . . . . . -40C to +85C
RECOMMENDED OPERATING CONDITIONS
ORDERING GUIDE
Model AD2S99AP AD2S99BP
*P = PLCC.
Temperature Range -40C to +85C -40C to +85C
Package Option* P-20A P-20A
NOTES 1 Pins 6 and 16 must be connected together. 2 Pins 19 and 20 must be connected together. 3 Resolver Reference two (EXC) is 180 phase advanced with respect to Resolver Reference one (EXC).
PIN CONFIGURATION
FBIAS SEL1 SEL2
3 NC SIN DGND COS NC 4 5 6 7 8 9
NC
2
1
20 19 18 EXC
VSS
VSS
AD2S99
TOP VIEW (Not to Scale)
17 EXC 16 AGND 15 NC 14 NC
10 11 12 13
SYNREF LOS VDD NC
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S99 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD2S99
CONNECTING THE AD2S99 OSCILLATOR
20 18 16
FREQUENCY - kHz
Refer to Figure 1. Positive supply voltage VDD should be connected to Pin 12 and negative supply voltage VSS should be connected to both Pins 19 and 20. Reversal of these power supplies will destroy the device. The appropriate voltage level for the power supplies is 5 V dc 5%. Both VSS Pins (19 and 20) must be connected together, and Digital Ground (Pin 6) must be connected to Analog Ground (Pin 16) locally at the AD2S99.
VSS 4.7F 0.1F
14 12 10 8 6 4 2
FBIAS
SEL1
SEL2
VSS
VSS
3 NC SIN DGND COS NC 4 5 6 7 8 9
2
1
20 19 18 17 EXC EXC AGND
RESOLVER REF SIN
0 0 4 8 12 16 20 24 ADDITIONAL RESISTANCE - k RESISTOR PULLUP TO VDD FROM FBIAS 28
AD2S99
16
Figure 2. Typical Added Resistance Value
COS
15 NC 14 NC 10 11 12 13
AD2S99 OSCILLATOR OUTPUT STAGE
NC SYNREF
LOS
VDD
NC
. .R* .X
100nF
TO AD2S80/ AD2S90 REF INPUT 100k
The output of the AD2S99 oscillator consists of two sinusoidal signals, EXC, and EXC. EXC is 180 phase advanced with respect to EXC. The excitation winding of a transducer should be connected across EXC (Pin 17) and EXC (Pin 18). With low impedance transducers, it may be necessary to increase the output current drive of the AD2S99. In such an instance, an external buffer amplifier can be used to provide gain (as needed), and additional current drive for the excitation output (either EXC or EXC) of the AD2S99, providing a single ended drive to the transducer. Refer to Figures 6, 7 and 8 for sample buffer configurations. The amplitude modulated SIN and COS output signals from a resolver should be connected as feedback signals to the AD2S99. The SYNREF output compensates for any primary to secondary phase errors in the resolver. These errors can degrade the accuracy of a Resolver-to-Digital Converter (R/D Converter). SIN, from the resolver, should be connected to the AD2S99 SIN input and COS should be connected to the AD2S99 COS input. The SIN Lo, COS Lo (resolver signal returns) should be connected to AGND and the R/D Converter as applicable. The synthesized reference (SYNREF) from the AD2S99 should be connected to the reference input pin of the R/D Converter. The SYNREF signal is a square wave at the oscillator frequency of amplitude 3 V p-p and is phase coherent with the SIN and COS inputs. If this signal is used to drive the reference input of the AD2S90 R/D Converter, a coupling capacitor and resistor to GND must be connected between the SYNREF output of the AD2S99 and the REF input of the R/D Converter (see Figure 3). Please read the appropriate R/D Converter data sheets for further clarification.
LOSS OF SIGNAL
50k
VDD
0.1F
4.7F
SEL2 = GND ] -5kHz MODE SEL1 = V SS ] INCREASE RX TO LOWER OUTPUT FREQUENCY (SEE GRAPH)
NC = NO CONNECT
*RX IS ONLY REQUIRED FOR INTERMEDIATE FREQUENCIES.
FIXED FREQUENCIES ONLY REQUIRE A LINK.
Figure 1. Typical Configuration
It is recommended that decoupling capacitors are connected in parallel between VDD and Analog Ground and VSS and Analog Ground in close proximity to the AD2S99. The recommended values for the decoupling capacitors are 100 nF (ceramic) and 4.7 F (tantalum). When multiple AD2S99s are used, separate decoupling capacitors should be used for each AD2S99.
FREQUENCY ADJUSTMENT
The output frequency of the AD2S99 is programmable to four standard frequencies (2, 5, 10, or 20 kHz) using the SEL1 and SEL2 pins. The output can also be adjusted to provide intermediate frequencies by connecting a resistor from the FBIAS pin to the positive supply VDD. The FBIAS pin is connected directly to VDD during normal operation. A graph showing the typical added resistance values for various intermediate frequencies is provided in Figure 2. The procedure for obtaining an intermediate frequency is: 1. Set the output frequency via the SEL1, SEL2 pins to the frequency immediately above the required intermediate frequency. 2. Connect the frequency adjust pin FBIAS to VDD via an external resistor. For example: to obtain an output frequency of 8 kHz, set the nominal output frequency to 10 kHz by connecting SEL1 to GND and SEL2 to VSS. Connect FBIAS to VDD via a 6 k resistor (refer to Figure 2).
During normal operation when both the SIN and COS signals on the resolver secondary windings are connected to the AD2S99, the LOS output pin of the AD2S99 (Pin 11) is at a Logic Lo (<0.7 V). If both the SIN and COS signals on the resolver secondary windings fall below the LOS threshold level of the AD2S99, the LOS pin of the AD2S99 will pull up to a Logic Hi (VDD) level.
-4-
REV. B
AD2S99
AD2S99/AD2S90 TYPICAL CONFIGURATION
Figure 3 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S90 Resolver-to-Digital Converter. The maximum level of the SIN and COS input signals to the AD2S90 should be 2 V rms 10%. All the analog ground signals should be star connected to the AD2S90 AGND pin. If shielded twisted pair cables are used for the resolver signals, the
shields should also be terminated at the AD2S90 AGND pin. The SYNREF output of the AD2S99 should be connected to the REF input pin of the AD2S90 via a 0.1 F capacitor with a 100 k resistor to GND. This is to block out any dc offset in the SYNREF signal. For more detailed information please refer to the AD2S90 data sheet.
VDD 0.1F
FBIAS SEL1 SEL2 VSS VSS
VSS 4.7F
NC = NO CONNECT NC 4 SIN 5 DGND 6 COS 7 NC 8
3
2
1
20 19 18 EXC EXC AGND
AD2S99
TOP VIEW (Not to Scale)
17 16
SEL2 = GND SEL1 = VSS FOUT = 5kHz
15 NC 14 NC
9 10 11 12 13
LOS VDD NC SYNREF NC
50k
VDD 0.1F 4.7F
0.1F
100k
18 17 16 15 14 S4 19 20 S2 S2 R2 REF R4 COS S4 S3 SIN S1 RESOLVER S1 4 POWER RETURN 5 S3 1 2 3 REF COS LO COS AGND SIN SIN LO VDD VDD 13 VSS 12 DGND 11
VDD 0.1F 0.1F 4.7F 4.7F VSS
AD2S90
TOP VIEW (Not to Scale) 6 7 8
10 9
Figure 3. AD2S99 and AD2S90 Example Configuration
REV. B
-5-
AD2S99
AD2S99/AD2S82A TYPICAL CONFIGURATION
Figure 4 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S82A Resolver-to-Digital Converter. The maximum level of the SIN and COS input signals to the AD2S82A should be 2 V rms 10%. All the analog ground signals should be star connected to the AD2S82A AGND pin. If shielded twisted pair cables are used for the resolver signals, the shields should also be terminated at the AD2S82A AGND pin.
Coupling capacitor C3, and resistor to GND R3, between the SYNREF output of the AD2S99 and the REF input pin of the AD2S82A are optional. For additional information on selecting component values for the AD2S82A, please refer to the AD2S82A data sheet or the application note "Passive Component Selection and Dynamic Modeling for the AD2S80 Series Resolver-to-Digital Converters" (AN-266).
SYNREF COS
R3, C3 OPTIONAL C3
VELOCITY OUTPUT R5
C5
R3 COS R2 -5V 4.7F SIN AGND 0.1F 3
FBIAS FBIAS
REF RESOLVER
SIN
C1 R1
C2 R4
C4
R6 6 7 8
SIG GND
AGND 0V 0.1F 39 -VS -12V 10F
5
A GND
4
COS I/P
3
AC ERROR O/P
2
DEMOD I/P
1
REFERENCE I/P
44 43 42 41 40
INTEGRATOR O/P DEMOD O/P INTEGRATOR I/P VCO O/P VCO I/P
2
SEL1
1
SEL2
20 19
VSS VSS
10F 18 17 16 EXC EXC AGND +12V
SIN I/P 0.1F +VS
38 RC 37 DIR 36 BUSY
SYNREF
NC 4 SIN 5 DGND 6 COS 7 NC 8
AD2S99
TOP VIEW (Not to Scale)
LOS VDD
NC 9 MSB DB1 10 DB2 11 DB3 12 DB4 13 DB5 14 DB6 15
35 DATA LOAD 34 COMP 33 SC2 32 SC1 DIGITAL GND 31
15 NC
NC
NC
14 NC
AD2S82A
TOP VIEW (Not to Scale)
9
10 11 12 13 0.1F 4.7F +5V LOS
LSB DB16
50k
DB7 16
DB13 DB10 DB11 DB12 DB9
ENABLE BYTE SELECT
30 INHIBIT 29 NC
NC = NO CONNECT
SEL1 = GND SEL2 = VSS FOUT = 10kHz
DIGITAL OUTPUT DATA DGND
18 19 20 21 22 23 24 25 26 27 28 +5V 0.1F 10F
Figure 4. AD2S99 and AD2S82A Example Configuration
+VL
DB8 17
DB14
DB15
-6-
REV. B
AD2S99
AD2S99/AD2S93 TYPICAL CONFIGURATION
Figure 5 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S93 LVDT-to-Digital Converter. The maximum level of the A and B transducer input signals to the AD2S93 should be 1 V rms 20%. All the analog ground signals should be star connected to the AD2S93 AGND pin. If shielded twisted pair cables are used for the LVDT signals, the
shields should also be terminated at the AD2S93 AGND pin. The SYNREF output of the AD2S99 cannot be used as the REF input signal for the AD2S93. The zero crossing reference for the AD2S93 should be taken from the primary winding of the LVDT through a phase lead or lag network. The phase compensation network ensures that the REF input is phase coherent with the A and B input signals to the AD2S93.
VDD 0.1F
FBIAS SEL1 SEL2 VSS VSS
VSS 4.7F
NC = NO CONNECT NC 4 SIN 5 DGND 6 COS 7 SEL2 = GND SEL1 = VSS FOUT = 5kHz NC 8
3
2
1 20 19 18 EXC EXC AGND
AD2S99
TOP VIEW (Not to Scale)
17 16
15 NC 14 NC
9 10 11 12 13
SYNREF LOS VDD NC NC
50k LOS 0.1F
VDD 4.7F
C1 R2 C2 R6 C3
C4
R5 PHASE COMP 25 24
REF NC
23 22
VEL INTIN
21 20 19
ACERROR DMODIN VGAIN
R7 18 VDD 17 VSS 16
26 27 B PRI SEC A LVDT 28 1 2 3 4
NC B A AGND DIFF GAIN LOS 5
DATA
DMODOUT VDD 0.1F 0.1F 4.7F 4.7F VSS
AD2S93
TOP VIEW (Not to Scale)
DGND 15 DIR 14 NULL 13 OVR 12
6
SCLK
7
CS
8
NC
9
UNR
10
CLKOUT
11
NC
NC = NO CONNECT
Figure 5. AD2S99 and AD2S93 Example Configuration
REV. B
-7-
AD2S99
FBIAS
FBIAS SEL1
SEL1
SEL2
SEL2
VSS
VSS
VSS
VOUT = 2VRMS
3 NC 4 SIN 5 DGND 6 COS 7 NC 8 9
NC
2
1
20 19 18 EXC EXC 17 16 AGND 15 NC 14 NC COS VOUT REF SIN
NC 4 SIN 5
3
2
1
20 19 18 EXC EXC 17 AGND 16 15 NC 14 NC
VSS
+VS
*
4 6 7 SSM2142 3 5 2 8
AD2S99
TOP VIEW (Not to Scale)
AD2S99
TOP VIEW (Not to Scale)
DGND 6 COS 7
RESOLVER
NC 8 9 10 11 12 13
*
SYNREF LOS VDD NC NC
10 11 12 13
SYNREF LOS VDD NC
NC = NO CONNECT
NC = NO CONNECT
-VS
*OPTIONAL; CONSULT APPROPRIATE
ANALOG DEVICES DATA SHEET.
Figure 6. Sample Buffer Configuration Figure 8. The SSM2142 as a Single Ended to Differential Driver
VOUT
R2 PIN 17 EXC VIN R1
PIN 16 AGND R2 VOUT = 2VRMS x - --- R1
OUTLINE DIMENSIONS
RESOLVER
Dimensions shown in inches and (mm).
(
)
PLCC (P-20A)
0.180 (4.57) 0.165 (4.19) 0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 8 9 0.020 (0.50) R 13 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 14
R2 PIN 18 EXC VIN R1 OP279 VOUT
0.048 (1.21) 0.042 (1.07)
0.056 (1.42) 0.042 (1.07) 19 PIN 1 IDENTIFIER TOP VIEW 18
PIN 16 AGND EXC PIN 17 R1
0.048 (1.21) 0.042 (1.07)
3 4
OP279 RESOLVER R2 R2 VOUT = 2VRMS x 2 x - --- R1
0.050 (1.27) BSC
(
)
A SUITABLE AMPLIFIER FOR ABOVE IS THE OP279
Figure 7. Sample Buffer Configurations
-8-
REV. B
PRINTED IN U.S.A.
C1978b-10-6/95
1

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